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? semiconductor MSM9225 1/73 general description the MSM9225 is a microcontroller peripheral lsi which conforms to the can protocol for high-speed lans in automobiles. features ?conforms to can protocol specification (bosch co., v.2.0 part b/full can) ? maximum 1 mbps real-time communication control (programmable) ? communication system: transmission line is bi-directional, two-wire serial communications nrz (non-return to zero) system using bit stuff function multi-master system broadcast system ? maximum 16 messages 8 bytes of message buffer number of messages can be extended by group message function (max: 2 groups) ? priority control by identifier normally 2032 types, 2032 2 18 types at extension ? microcontroller interface corresponding to both parallel and serial interface parallel interface: separate address/data bus type (with address latch signal/no address latch signal) and multiplexed address/data bus type. serial interface: synchronous communication type interrupt is used for three outputs: transmission/receive/error ? error control: bit error/stuff error/crc error/form error/acknowledge error detection functions retransmission / error status monitoring function when error occurs ? communication control by transmission request function ? sleep/stop mode function ? supply voltage: 5 v 10% ? operating temperature: -40 to +115?c ? package: 44-pin plastic qfp (qfp44-p-910-0.80-2k) (product name: MSM9225ga-2k) e2f0016-19-43 this version: aug. 1998 ? semiconductor MSM9225 can (controller area network) controller preliminary this version: apr. 1999
? semiconductor MSM9225 2/73 block diagram rx0 tx0 tx1 rx1 v dd gnd bit stream logic (bsl) transmission control logic (tcl) error management logic (eml) bit timing logic (btl) data memory data manege- ment logic receive control logic (rcl) xt xt reset timing generator microcontroller interface 8 av dd agnd serial i/f parallel i/f a7-0 8 ad7-0/d7-0 pale pwr prd /sr w prdy /swait r w wait sclk sdi sdo rd rdy mode1, 0 cs int configuration example can abs engine controller can can transmission automatic air conditioner can seat-position controller can can outside mirror controller can power window suspention can can bus power steering can
? semiconductor MSM9225 3/73 pin configuration (top view) 44-pin plastic qfp 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 a4 a5 a6 a7 sdo gnd sdi sclk prd /sr w cs int ad2/d2 ad1/d1 ad0/d0 mode1 mode0 gnd pale pwr reset v dd tx1 44 43 42 41 40 39 38 37 36 35 34 a3 a2 a1 a0 v dd gnd ad7/d7 ad6/d6 ad5/d5 ad4/d4 ad3/d3 12 13 14 15 16 17 18 19 20 21 22 v dd xt xt gnd prdy /swait agnd rx0 rx1 av dd gnd tx0
? semiconductor MSM9225 4/73 pin descriptions symbol type cs i description chip select pin. when "l", pale, pwr , prd /sr w , sclk and sdo pins are valid. pin 10 a7-0 i address bus pins (when using separate buses). if used with a multiplexed bus or if used in the serial mode, fix these pins at "h" or "l" levels. 41-44, 1-4 ad7-0 /d7-0 i/o multiplexed bus: address/data pins separate buses: data pins if used in the serial mode, fix these pins at "h" or "l" levels. 31-38 pwr i write input pin during parallel mode. data is captured when this pin is at a "l" level. if used in the serial mode, fix this pin at a "h" or "l" level. 26 rpd /sr w i parallel mode: read signal pin. when at a "l" level, data is output from the data pin. serial mode: read/write signal pin. when at a "h" level, data is output from the sdo pin. when at a "l" level, the sdo pin is at high impedance, and data is captured beginning with the second byte of data input from the sdi pin. 9 pale i address latch signal pin. when at a "h" level, addresses are captured. if used in the parallel mode and the address latch signal is unnecessary or in the serial mode, fix this pin at a "h" or "l" level. 27 sdi i serial data input pin. addresses (1st byte) and data (beginning from the 2nd byte) are input to this pin, lsb first. if used in the parallel mode, fix this pin at a "h" or "l" level. 7 sdo o serial data output pin. when the cs pin is at a "h" level, this pin is at high impedance. when cs is at a "l" level, data is output from this pin lsb first. if used in the parallel mode, fix this pin at a "h" or "l" level. 5 sclk i shift clock input pin for serial data. at the rising edge of the shift clock, sdi pin data is captured. at the falling edge, data is output from the sdo pin. 8 prdy /swait o ready output pin. if the microcontroller's bus cycle is fast, a signal is output to extend the bus cycle until the internal access is completed. 16 parallel mode serial mode internal access in progress after completion of access "l" level output high impedance output "h" level output "l" level output
? semiconductor MSM9225 5/73 symbol type description pin mode1, 0 i microcontroller interface select pins. 29, 30 mode1 0 1 1 0 mode0 0 1 0 1 parallel mode serial mode separate buses no address latch signal with address latch signal multiplexed buses interrupt request output pin. when an interrupt request occurs, a "l" level is output. three types of interrupts share this pin: transmission complete, reception complete, and error. int o 11 reset pin. system is reset when this pin is at a "l" level. reset i 25 clock pins. if internal oscillator is used, connect a crystal oscillator. if external clock is input, input clock via xt pin. the xt pin should be left open. xt i 13 xt o 14 receive input pin. differential amplifier included. rx0, rx1 i 18, 19 transmission output pin. tx0, tx1 o 22, 23 internal logic power supply pin. v dd 12, 24, 40 internal logic gnd pin. gnd 6, 15, 21 28, 39 power supply pin for receive input differential amplifier. av dd 20 gnd pin for receive input differential amplifier. agnd 17 interface
? semiconductor MSM9225 6/73 functional description data memory before starting communication, messages for communication and various control registers must be set at the data memory. addresses x0hex to xdhex are the message memory, which stores control registers, identifiers and the contents of each message. in this address space, the higher 4 bits of an address corresponds to the number of messages, and a maximum of 16 (0xhex to fxhex) can be stored. each message has an area to store a maximum of 8 bytes of data memory, 1 byte of control register, and a maximum of 5 bytes of an identifier. this means that the data memory capacity for messages is: 16 messages (8 bytes for a message + 1 byte for a control register + 5 bytes for an identifier) = 224 bytes. addresses xehex to xfhex are allocated to the control registers. the configuration of data memory is as follows data memory configuration address function message control register identifier 0 identifier 1 message 0 identifier 2 message 1 identifier 3 message 2 identifier 4 message 3 message 0 message 4 message 1 message 5 message 2 message 6 message 3 message 7 message 4 message 5 message 6 message 7 various control registers a7 a6 a5 a4 a3 a2 a1 a0 idfm = 0 (standard) idfm = 1 (extended) 0000 0 corresponds to number of messages 001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 1111 0000 1111
? semiconductor MSM9225 7/73 message memory the message memory stores messages to be transmitted/received. for transmission, only messages stored in the message memory can be transmitted. a message with the highest priority among messages requested for transmission is sent. for receiving, only messages that have an identifier stored in the message memory can be received. when a message is received normally, and its identifier matches with the identifier stored in the message memory, data of the received message is written to the message area of the corresponding message in the message memory. the message memory can store a maximum of 16 messages. set messages at the nmes register. 1. inside message control register (x0hex) this register performs various controls for a message. set this register for each message. the bit configuration is as follows: 76543210 address msb 0h lsb ares : automatic transmission frm : message format setting eit : transmission completion interrupt enable eir : receive completion interrupt enable rcs : receive status trq : transmission request not used mma : message memory access enable (1) message memory access request/enable bit: mma this bit prevents contention between the microcontroller and can when accessing the message memory. when the microcontroller accesses the message memory, "1" is written to the mma bit regularly. the microcontroller confirms that the mma bit is "1", and then accesses the message memory. write "0" to the mma bit when the microcontroller accessing ends. operations by the mma bit are shown in the following table. at reset, the mma bit is set to "0". mma 0 1 accesses from microcontroller to message memory are disabled accesses from microcontroller to message memory are enabled operate reading of received data reception stop rewriting of control area operate transmission stop rewriting of control area rewriting of transmission data microcontroller
? semiconductor MSM9225 8/73 (2) transmission request: trq when a message is transmitted, the microcontroller writes "1" to this bit. when transmission ends normally, can writes "0". this means that the trq bit is "1" during transmission. therefore, to request transmission, confirm that the trq bit is "0" first, then write "1" to the trq bit. when the remote frame is received while the ares bit is "1", the trq bit is set to "1". at reset, the trq bit is set to "0". (3) receive status: rcs when receiving completes, the rcs bit becomes "1". write "0" to the rcs bit before the microcontroller calls up receive data. when receiving the remote frame, the rcs bit becomes "1" just after the reception. at reset, the rcs bit is set to "0". (4) receive completion interrupt enable: eir the microcontroller sets interrupt request signal generation disable/enable when receiving completes. the eir bit is valid when the eintr bit of the cani register is 1. at reset, the eir bit is set to "0". (5) transmission completion interrupt enable: eit the microcontroller sets interrupt request signal generation disable/enable when transmission completes. the eit bit is valid when the eintt bit of the cani register is 1. at reset, the eit bit is set to "0". (6) message format setting: frm the microcontroller sets the format of the message to be sent/received. a message in a format other than the specified format cannot be sent/received. for the relationship between setting and format, see the table below. when a message specified to a group message is received, the content of the rtr bit is written. at reset, the frm bit is set to "0". frm message type transmission format receive format 0 1 standard message data frame remote frame group message transmission disable data frame remote frame transmission disable data frame remote frame standard message group message (7) automatic transmission : ares if the data frame is automatically transmitted after remote frame reception, the ares bit should be set to "1". at reset, the ares bit is set to "0".
? semiconductor MSM9225 9/73 2. identifier 0 (x1hex) this register sets the data length code and a part of the identifier. set this register for each message. the bit configuration is as follows: (1) format setting: idfm the microcontroller sets the message format. at reset, the idfm bit is undefined. idfm operation 0 standard format (id = 11 bits) extended format (id = 29 bits) i (2) data length code: dlc3 to dlc0 this is control field data to set the number of bytes of a data field. 0 to 8 can be set. at reset, these bits are undefined. (3) identifier: idb28 to idb26 these bits set the identifier field. for standard format (idfm = 0), the higher 3 bits of the 11 bits are set. for extended format (idfm = 1), the higher 3 bits (id28 to id26) of the 29 bits (id28 to id0) are set. at reset, these bits are undefined. 76543210 address msb 1h lsb idb26 : idb27 : idb28 : dlc0 : dlc1 : dlc2 : dlc3 : idfm : format settin g identifier data length code
? semiconductor MSM9225 10/73 3. identifier 1 (x2hex) this register sets the identifier. set this register for each message. the bit configuration is as follows: 76543210 address msb 2h lsb idb18 : idb19 : idb20 : idb21 : idb22 : idb24 : idb25 : idb23 : identifier (1) identifier: idb25 to idb18 these bits set the lower 8 bits of the 11 bits of the identifier field. for standard format (idfm = 0), the lower 8 bits of the 11 bits are set. for extended format (idfm = 1), id25 to id18 of the 29 bits (id28 to id0) are set. at reset, these bits are undefined. 4. address: x3 to xdhex for standard format (idfm = 0), addresses x3 to xahex become the transmission/receive data storage area. for extended format (idfm = 1), addresses x3 to x5hex are used to set the identifier field, and addresses x6 to xdhex become the transmission/receive data storage area. for both, a maximum of 8 bytes of transmission/receive data can be stored, but the number of transmittable/receivable bytes must have been set by data length code. at reset, message content is undefined. the relationship between address and identifier bits for extended format (idfm = 1) is as follows:
? semiconductor MSM9225 11/73 76543210 adderss msb 3h lsb idb10 : idb11 : idb12 : idb13 : idb14 : idb16 : idb17 : idb15 : identifier 2 76543210 address msb 4h lsb idb2 : idb3 : idb4 : idb5 : idb6 : idb7 : idb8 : idb9 : identifier 3 76543210 address msb 5h lsb not used (don't care) not used (don't care) not used (don't care) not used (don't care) not used (don't care) not used (don't care) idb0 : idb1 : identifier 4
? semiconductor MSM9225 12/73 control register these registers listed below control various operations of can. address symbol 0eh canc 0fh cani name can control register can interrupt control register 1eh nmes number of message specification registers 1fh btr0 can bus timing register 0 2eh btr1 can bus timing register 1 2fh tioc communication input/output control register 3eh gmr0 group message register 0 3fh gmr1 group message register 1 4eh gmsk00 message mask register 00 4fh gmsk01 message mask register 01 5eh gmsk02 message mask register 02 5fh gmsk03 message mask register 03 6eh gmsk10 message mask register 10 6fh gmsk11 message mask register 11 7eh gmsk12 message mask register 12 7fh gmsk13 message mask register 13 8eh stby standby control register 8fh not used (reserve area) 9eh tmn communication message number register 9fh cans can status register aeh tec transmission error counter afh rec receive error counter beh bfh ceh cfh deh dfh eeh efh feh ffh not used (reserve area)
? semiconductor MSM9225 13/73 1. can control register (canc: 0ehex) this register controls the operation of can. the bit configuration is as follows: 76543210 address msb 0eh lsb init : initialize tirs : transmission identifier retrieval not used sync : bit synchronization cana : can write flag t x f : transmission flag r x f : receive flag not used (1) initialize: init this bit is used to initialize the communication control area. to start initialization, write "1" to init, read init and confirm that init is "1", then initialize. to end initialization, write "0" to init, read init, and confirm that init is "0". for both, initialization mode is not set/cleared until the above procedure is executed. if the init bit is set to "1" during the transmission or receive operation, the initialization will start after the communication completes. when the init bit is set to "1", the communication operation stops but the error counter and data memory are held. to initialize message memory, write the number of messages to be used to the number of messages setting register, nmes, then write the inside message control register, identifier 1, and identifier 2 sequentially from message 0 for all messages. at reset, init is set to "1". (2) transmission identifier retrieval: tirs this bit is used to scan identifiers sequentially from message 0 to the last message of the message memory, detecting priority of the message for which the transmission request trq is "1" and starting to transmit the messages. tirs will be set to "0" when there are no transmission request messages after scanning or transmitting. at reset, tirs is set to "0". (3) bit synchronization: sync this bit is used to set the bit synchronization edge to synchronize at the can bus. when sync is "0", the synchronization edge is set at the falling edge of data. when sync is "1", the synchronization edge is set at both the rising and falling edges of data. at reset, sync is set to "0".
? semiconductor MSM9225 14/73 (4) can write flag: cana this bit is used to indicate receive data write status to the message memory. cana is "1" while can is writing receive data to the message memory. this is a read-only flag. (5) transmission flag: txf this bit is used to indicate transmission operation status. when txf is "0", can is in transmission operation stop status. when txf is "1", can is in transmission operation status. txf becomes "0" when transmission completes. this is a read-only flag. (6) receive flag: rxf this bit is used to indicate receive operation status. when rxf is "0", can is in receive operation stop status. when rxf is "1", can is in receive operation status. rxf becomes "0" when receiving completes. this is a read-only flag. 2. can interrupt register (cani: 0fhex) this register controls can interrupts. the bit configuration is as follows: (1) transmission interrupt output enable: eintt this bit is used to output transmission interrupt signal intt from interrupt pin int when transmission completes. when eintt is "0", a transmission interrupt signal is not output from the interrupt pin. when eintt is "1", a transmission interrupt signal is output from the interrupt pin. at reset, eintt is set to "0". (2) receive interrupt output enable: eintr this bit is used to output receive interrupt signal intr from interrupt pin int when reception completes. when eintr is "0", a receive interrupt signal is not output from the interrupt pin. when eintr is "1", a receive interrupt signal is output from the interrupt pin. at reset, eintr is set to "0". 76543210 address msb 0fh lsb eintt : transmission interrupt output enable eintr : receive interrupt output enable einte : error interrupt output enable not used itf : transmission interrupt request flag irf : receive interrupt request flag ief : error interrupt request flag meint : master interru p t control enable
? semiconductor MSM9225 15/73 (3) error interrupt output enable: einte when an error occurs, this bit is used to output error interrupt signal inte from interrupt pin int . when einte is "0", an error interrupt signal is not output from the interrupt pin. when einte is "1", an error interrupt signal is output from the interrupt pin. at reset, einte is set to "0". (4) transmission interrupt request flag: itf itf becomes "1" when a transmission interrupt is generated. only "0" can be written to this bit. at reset, itf is set to "0". (5) receive interrupt request flag: irf irf becomes "1" when a receive interrupt is generated. only "0" can be written to this bit. at reset, irf is set to "0". (6) error interrupt request flag: ief ief becomes "1" when an error occurs. only "0" can be written to this bit. at reset, ief is set to "0". (7) master interrupt control enable: meint this bit is used to set enable/disable of communication interrupts. the flowchart of interrupt control is shown below. when meint is "0", interrupt request control is disabled. when meint is "1", interrupt request control is enabled. at reset, meint is set to "0". eit (each message) itf interrupt factor (transmission completion) eintt 1 0 eir (each message) irf interrupt factor (reception completion) eintr 1 0 einte 1 0 ief interrupt factor (an error occurs) meint 1 0 int pin
? semiconductor MSM9225 16/73 address msb 1eh *** nmes3 nmes2 nmes1 nmes0 lsb number of message **** 0000 **** 1110 **** 0000 **** 1111 1 2 15 16 * : don't care * 3. number of messages specification register (nmes: 1ehex) this is a register to set the number of messages to be stored in the message memory. a maximum of 16 messages can be set, with message numbers 0 to 15. writing to nmes is enabled when initialize bit init of the can control register (canc: oehex) is "1". at reset, nmes is set to "0000". the bit configuration and relationship between message number and number of messages are as follows: 4. can bus timing register 0 (btr0: 1fhex) this register sets the baud rate prescaler and synchronization jump width (sjw) used for bus timing. writing to the btr0 bit is enabled, when the init bit of the can control register (canc: 0ehex) is "1". the bit configuration is as follows: 76543210 address msb 1fh lsb brp0 : brp1 : brp2 : brp3 : brp4 : brp5 : sjwa : sjwb : baud rate prescaler synchronization jump width
? semiconductor MSM9225 17/73 brp5 brp3 brp2 brp1 brp0 00001 00000 11110 btl cycle time 1 brp4 0 0 1 11111 1x system clock cycle 2x system clock cycle 63x system clock cycle 64x system clock cycle (1) baud rate prescaler: brp5 to brp0 this is a 6-bit prescaler to set the btl cycle time and sjw of the basic clock for communication operation. the relationship between the bit content and btl is as follows: at reset, brp5 to brp0 are set to "000000". the btl cycle time is given by the following operation. btl cycle time = 2 (2 5 brp5 + 2 4 brp4 + 2 3 brp3 + 2 2 brp2 + 2 1 brp1 + brp0 + 1)/f osc *) system clock is 1/2 division of oscillation frequency. f osc is the oscillation frequency. (2) sjw: sjwa, sjwb this is a 2-bit register to set sjw. the relationship between bit content and sjw is as follows: at reset, sjwa and sjwb are set to 00. sjwb sjwa sjw1, sjw2 001 btl cycle 012 btl cycle 103 btl cycle 114 btl cycle
? semiconductor MSM9225 18/73 (1) time segment 1: tseg13 to tseg10 this is a 4-bit register to set the sampling point. the relationship between bit content and tseg1 is as follows: at reset, tseg13 to tseg10 are set to "0000". (2) time segment 2: tseg22 to tseg20 this is a 3-bit register to set the transmit point. the relationship between the bit content and tseg2 is as follows: at reset, tseg22 to tseg20 are set to "000". tseg13 tseg12 tseg11 tseg10 tseg1 0000 0001 1110 1111 1 btl cycle 2 btl cycle 15 btl cycle 16 btl cycle tseg22 tseg21 tseg20 tseg2 000 001 110 111 1 btl cycle 2 btl cycle 7 btl cycle 8 btl cycle 5. can bus timing register 1 (btr1: 2ehex) this register sets the sampling count, sampling point and transmit point used for bus timing. writing to the btr1 bit is enabled, when the init bit of the can control register (canc: 0ehex) is "1". the bit configuration is as follows: 76543210 address msb 2eh lsb tseg10 : tseg11 : tseg12 : tseg13 : tseg20 : tseg21 : tseg22 : not used : time segment 1 time segment 2
? semiconductor MSM9225 19/73 if setting is : btr0 = "01000001" ...sjwb = "0" sjwa = "1" brp5-0 = "000001" btr1 = "00000001"...tseg2 = "000" tseg1 = "0001" then the bit timing is as follows sync segment 1 btl cycle (fixed) sjw 1 2 btl cycle tseg 1 2 btl cycle tseg 2 1 btl cycle sjw 2 2 btl cycle 1 bit time 8 btl cycle sampling point = 5 btl cycle if f osc = 16 mhz, then 1 btl cycle is : btl cycle = 2 (2 5 0 + 2 4 0 + 2 3 0 + 2 2 0 + 2 1 0 + 1 + 1) / 16 mhz = 0.25 m s therefore 1 bit time is : 8 btl cycle = 8 0.25 m s = 2.0 m s (= 500 kb/s) 6. communication input/output control register (tioc: 2fhex) this register sets the communication mode and output buffer format. writing to the tioc bit is enabled, when the init bit of the can control register (canc: 0ehex) is "1". the bit configuration is as follows: (3) bit timing bit timing is set by can bus timing registers 0 and 1. the relationship between 1 bit time of a message and a can bus timing (the MSM9225 register) is as follows: 1 bit time sjw1 (btr0 : sjwb/a) tseg1 (btr1 : tseg13-10) tseg2 (btr1 : tseg22-20) sjw2 (= sjw1) 1btl cycle sampling point prop-seg sync-seg phase-seg1 phase-seg2
? semiconductor MSM9225 20/73 76543210 address msb 2fh lsb ocmd0 ocmd1 ocpol0 octn0 octp0 ocpol1 octn1 octp1 : : : : : : : : output mode setting tx0 output buffer format tx1 output buffer format (1) time segment 1: ocmd1 to ocmd0 these bits are used to set the output mode of output pins tx0 and tx1. the relationship between the bit content and output mode is as follows: at reset, ocmd1 to ocmd0 are set to 00. ocmd1 ocmd0 [double layer mode] transmission data "0" is output from tx0 and tx1 altermately. data tx0 tx1 101010 00 01 10 11 [single layer mode] same bit string data is output from both tx0 qnd tx1. data tx0 tx1 101010 [disabled] [clock output mode] bit string data is output from tx0. synchrinization clock is output from tx1. data tx0 tx1 101010 output example output example output example output mode of tx0 and tx1
? semiconductor MSM9225 21/73 circuit configuration output control circuit output data synchronization clock v dd p ch tx0 n ch gnd v dd p ch tx1 n ch gnd (2) output driver format setting: ocpol, octn, octp ocpol is used to set the polarity of output. octn is used to set the open/drain mode of the nch transistor of the output driver. octp is used to set the open/drain mode of the pch transistor of the output driver. the circuit configuration of the output driver and the relationship between bit content and output driver format are as follows: at reset, all bits are set to "0".
? semiconductor MSM9225 22/73 mode octp octn ocpol output data pch tr nch tr tx pin output level floating pulldown pullup push-pull 0 0 0 0 off off 0 0 0 1 off off 0 0 1 0 off off 0 0 1 1 off off 0 1 0 0 off on 0 1 0 1 off off 0 1 1 0 off off 0 1 1 1 off on 1 0 0 0 off off 100 1 onoff 101 0 onoff 1 0 1 1 off off 1 1 0 0 off on 110 1 onoff 111 0 onoff 1 1 1 1 off on floating floating floating floating "0" floating floating "0" floating "1" "1" floating "0" "1" "1" "0" output driver format
? semiconductor MSM9225 23/73 7. group message register (gmr0: 3ehex, gmr1: 3fhex) these are registers to set the group message mode. two messages can be set to the group message mode. at reset, all bits are set to "0". the group message mode is valid when the egm0/egm1 bit is "1". using gmr03 to gmr00 and gmr13 to gmr10, set the message numbers of messages that are to be set to the group message mode. the bit configuration is as follows: address msb 3eh lsb 3fh egm0 0 0 0 gmr03 gmr02 gmr01 gmr00 egm1 0 0 0 gmr11 gmr12 gmr11 gmr10 gmr0 gmr1 8. group message mask register (gmsk) this is a register to judge identifiers when a message with a message number specified by the group message mode gmr is received. using miid28 to miid0, set the bits to mask the identifier of a message set by the gmr bit. setting "1" masks the bit, setting "0" does not mask the bit. (m0id28 to m0id0 are for gmr0, and m1id28 to m1id0 are for gmr1.) at reset, all bits are set to "0". the bit configuration is as follows: address msb 4eh lsb 4fh m0id28 m0id27 m0id26 m0id25 m0id24 m0id23 m0id22 m0id21 m0id20 m0id19 m0id18 m0id17 m0id16 m0id15 m0id14 m0id13 gmsk00 gmsk01 5eh 5fh m0id12 m0id11 m0id10 m0id9 m0id8 m0id7 m0id6 m0id5 m0id4 m0id3 m0id2 m0id1 m0id0 0 0 0 gmsk02 gmsk03 address msb 6eh lsb 6fh m1id28 m1id27 m1id26 m1id25 m1id24 m1id23 m1id22 m1id21 m1id20 m1id19 m1id18 m1id17 m1id16 m1id15 m1id14 m1id13 gmsk10 gmsk11 7eh 7fh m1id12 m1id11 m1id10 m1id9 m1id8 m1id7 m1id6 m1id5 m1id4 m1id3 m1id2 m1id1 m1id0 0 0 0 gmsk12 gmsk13
? semiconductor MSM9225 24/73 9. standby control register (stby: 8ehex) this register sets various modes, such as stop mode. the bit configuration is as follows: 76543210 address msb 8eh lsb stop : stop mode sleep : sleep mode not used not used not used not used not used not used (1) stop mode: stop if stop is set to "1", the MSM9225 will enter the stop mode when the can bus is idle. in stop mode, the content of data memory is held but the oscillator and all circuits stop to save power consumption. access to/from external units is therefore disabled. stop mode is cleared by a reset signal input from the reset pin or cs pin = "0". at reset, stop is set to "0". (2) sleep mode: sleep if sleep is set to "1", the MSM9225 will enter the sleep mode when the can bus is idle. in sleep mode, the content of data memory is held and the differential input of rx0 and rx1 operates, but the oscillator and other circuits stop operation. access to/from external units is therefore disabled. sleep mode is cleared by a reset signal input from the reset pin or cs pin = "0", or by the differential input of rx0 and rx1. when both stop mode and sleep mode are set at the same time, the MSM9225 enters stop mode. at reset, sleep is set to "0".
? semiconductor MSM9225 25/73 10. communication message number register (tmn: 9ehex) the communication message number is recorded in this register. the bit configuration is as follows: (1) transmission message number register: trsn3 to trsn0 this is a register to store the message number when a message is transmitted/received. when transmission completes, the transmitted message number is stored. when receiving completes, the received message number is stored. and when an error occurs, the message number of the message being transmitted/received at that time is stored. this is a read-only register and is set to "0000" at reset. 76543210 address msb 9eh lsb trsn0 : trsn1 : trsn2 : trsn3 : not used not used not used not used transmission message number register
? semiconductor MSM9225 26/73 11. can status register (cans: 9fhex) this is a status register to indicate the status of can. bit6 to bit4 are flags for the transmitter and bit1 and bit0 are for the receiver, and this register is read only. the bit configuration is shown below. (1) receiver error warning: rew when the receiver error counter (rec) 3 96, rew becomes "1". if rew = "1", the bus may be seriously damaged. the bus must be tested for this condition. at reset or when rec < 96, rew becomes "0". (2) receiver error passive: rep when the receive error counter (rec) 3 128, rep becomes "1". at reset or when rec < 128, rep becomes "0" (error active) (3) transmitter error warning: tew when the transmit error counter (tec) 3 96, tew becomes "1". if tew = "1", the bus may be seriously damaged. the bus must be tested for this condition. at reset or when tec < 96, tew becomes "0". (4) transmitter error passive: tep when the transmit error counter (tec) > 128, tep becomes "1". at reset or when tep < 128, tep becomes "0". (5) bus off: boff this flag indicates the can bus status. when the transmit error counter (tec) > 256 boff becomes "1" and the can bus is in the bus off state. at reset or when tep < 256, boff becomes "0". 76543210 address msb 9fh lsb rew : receiver error warning rep : receiver error passive not used not used tew : transmitter error warning tep : transmitter error passive boff : bus off flag not used
? semiconductor MSM9225 27/73 12. transmit error counter (tec: aehex) tec indicates the lower 8 bits of the 9-bit transmit error counter. the bit configuration is shown below. at reset, tec is set to "0000 0000". the relation between the transmit error counter and tec is shown below. 76543210 transmit error counter tec (aeh) tep (cans: bit5) 0: error active state 1: error p assive state 8 boff (cans: bit6) 1: bus off state 76543210 address msb aeh lsb tec0 : tec1 : tec2 : tec3 : tec4 : tec5 : tec6 : tec7 : transmit error counter
? semiconductor MSM9225 28/73 13. receive error counter (rec: afhex) the receive error counter is read-only. the bit configuration is shown below. 76543210 address msb afh lsb rec0 : rec1 : rec2 : rec3 : rec4 : rec5 : rec6 : rec7 : receive error counter at reset, rec is set to "0000 0000". the relation between the receive error counter and each register is shown below. 76543210 receive error counter rec (afh) rep (cans: bit1) 0: error active state 1: error p assive state
? semiconductor MSM9225 29/73 operational description MSM9225 operation is described below. operational procedure procedures to set and operate various communication protocols are indicated below. 1. initial setting the initial setting procedure is indicated below. start initial setting set init bit of canc register (0ehex) to "1" read init bit init = 1? set the number of messages with the nmes register (1ehex) set the inside message control register (x0hex) set the message unit (frm/dcl3-dcl0, /id28-id0) all message settings complete? set the interrupt control with the cani register (0fhex) initial setting complete set init bit of the canc register (0ehex) to "0". group message settings (gmr/gmsk) set tx0, tx1, rx0, rx1 states with the tioc register (2fhex) can bus timing settings btr0 (1fhex) btr1 (2ehex) yes yes no no *) since the init bit cannot be set to "1" during transmission or reception, read and verify its value.
? semiconductor MSM9225 30/73 2. transmit procedure the transmit procedure is indicated below. start transmit setting set mma bit of the inside message control register (x0hex) to "1" read mma bit mma = 1? set inside message control register's mma = 0 and trq = 1 set tirs bit of canc register (0ehex) to "1" yes no *) since the mma bit cannot be set to "1" while the message is being accessed, read and verify its value. transmit setting complete transmission operation write message data to data memory all transmit message settings complete? yes no set tirs bit of canc register (0ehex) to "0"
? semiconductor MSM9225 31/73 3. receive procedure the receive procedure is indicated below. receive procedure yes (MSM9225) interrupt signal is generated when reception is complete int : 1 ? 0 verify that irf bit of cani register (0fhex) is "1" set irf bit of cani register (0fhex) to "0" verify reception message number with tmn register (9ehex) set rcs bit of inside message control register (x0hex) to "0" read reception data from data memory inside message control register's rcs = 0? canc register's (0ehex) cana = 0? receive complete yes no *) check whether new reception data has been written to the same message while data was being read. no *) check whether reception data has been written to another message while data was being read. this step may be omitted and evaluation performed based on the interrupt signal. *) verify that the interrupt is caused by the reception completion.
? semiconductor MSM9225 32/73 4. message unit rewrites during operation the procedure to rewrite the identifier (id) and data length code (dlc) during operation is indicated below. the number of messages set in the nmes register at the initial setting is the number of (valid) messages that may be rewritten. start rewrite set mma bit of inside message control register (x0hex) to "1" read mma bit mma = 1? rewrite message unit frm/dlc3-dlc0/id28-id0 set mma bit of inside message control register to "0" rewrite complete yes no all message settings complete? yes no
? semiconductor MSM9225 33/73 5. remote frame operation the following two methods are available for transmission after remote frame reception. (1) automatically transmit message data that has been previously set (2) set message data and then transmit 5-1. automatic response after remote frame reception, this method automatically transmits previously set message data. settings of the inside message control register are listed in the table below. bit symbol value comments 5 trq 0* 3 eir 2 eit 1 1 frm 0 0 ares 1 when reception is complete, trq bit changes from 0 ? 1 set transmit interrupt to verify the end of transmission. set the remote frame. set automatic response. inside message control register a flow chart of the operation is shown on the following page.
? semiconductor MSM9225 34/73 microcontroller (user) operation MSM9225 operation start automatic response set mma bit of inside message control register (x0hex) to "1" mma = 1? yes no read mma bit set the inside message data register (x0hex) as shown in previous table remote frame reception? yes no write transmit data to data memory set mma bit to "0" data frame transmission transmission completion generates interrupt int : 1 ? 0 verify that itf bit of canc register (0fhex) is "1" set itf bit to "0" set rsc bit of inside message control register to "0" transmit data setting remote reception and transmission remote transmission verification figure: automatic response operation flow chart
? semiconductor MSM9225 35/73 5-2. manual response in this method, after remote frame reception, the transmit data is set and then transmission begins. settings of the inside message control register are listed in the table below. a flow chart of the operation is shown on the following page. the basic operation is a combination of receive and transmit procedures. bit symbol value comments 5 trq 0 3 eir 1 2 eit 1 1 frm 0 0 ares 0 set to receive message. set interrupt to verify the end of transmission. set the remote frame. specify that there will be no automatic response. inside message control register set interrupt to verify (remote frame) reception.
? semiconductor MSM9225 36/73 start manual response verify reception interrupt with cani retgister (0fhex) mma = 1? yes no remote frame reception? yes no data frame transmission message reception generates interrupt int : 1 ? 0 verify transmission is complete remote reception transmit data setting remote transmission verify receive message number with tmn retgister (9ehex) set rcs bit of inside message control register (x0hex) to "0" set mma bit of inside message control register to "1" set inside message control registers mma = 0 and trq = 1 set tirs bit of canc register (0ehex) to "1" transmission completion generates interrupt int : 1 ? 0 write transmit data to data memory microcontroller (user) operation MSM9225 operation figure: manual response operation flow chart
? semiconductor MSM9225 37/73 operation at receiving message 1. priority of message a message has the priority determined by the identifier setting. to determine priority, identifiers of messages are compared from the higher bit, and the identifier (set to "0") detected first has the higher priority. (see the example below) identifier (example) 0 01 10101 priority 0 01 10101 0 00000101 0 00101101 second first fourth third in this exam p le, p riorit y is determined at the shaded bits. 00 1 00 0 10 01 2. data length code when the received data length code (hereafter dlc) matches the dlc being set to the message memory, the number of bytes of data indicated by the received dlc is received and written to the message memory. when the received dlc does not match with the dlc being set to message memory, the MSM9225 operates as follows: (1) received dlc > dlc on message memory the number of bytes of data indicated by the dlc on the message memory is received and written to the message memory. the data exceeding the number of bytes indicated by dlc on the memory is not written to message memory. (2) dlc on message memory > received dlc the number of bytes of data indicated by the received dlc is received and written to the message memory. 3. group message function if the group message function is used, a part of an identifier can be masked. this can increase the number of receivable identifiers. to use the group message function, set the message number of the target message to set the group message function at the gmr register. then set the bits to be masked at the gmsk register. depending on the location of bits to be masked, an another identifier being set at the message memory may be received. in this case, the priority of identifiers being set on the message memory is calculated and the identifier having the highest priority is received. the received data is written to the message memory indicated by the message for which the identifier with the highest priority is set.
? semiconductor MSM9225 38/73 when same identifiers are set to multiple messages on message memory when same identifiers are set to multiple messages on the message memory, operations are as follows. 1. transmit operation messages are transmitted sequentially from the smaller message number. 2. receive operation the message is always written to the smallest message number. for example, the same identifier is set at message numbers 1 to 4, as shown below. identifier (example) 0 01 11111 the range in which the same identifier is set. 00 1 0 00000111 00 0 00000011 10 message number 0 1 2 3 4 5 6 11 1 11 11 1 00111001 11 1 00 11001 1 00111001 1 00111001 ? transmit operation if every message above is a transmit message, messages are transmitted sequentially in the order of message number 5 ? 0 ? 6 ? 1 ? 2 ? 3 ? 4. ? receive operation when the identifier "11100111001" is received from the can bus, received data is always written to the message memory which is indicated by the message number 1.
? semiconductor MSM9225 39/73 microcontroller interface there are basically two methods of interfacing to the microcontroller. (1) synchronous serial interface (serial mode) (2) parallel bus interface (parallel mode) each interface is selected with the mode0 and mode1 pins. refer to the section, pin descriptions, "pin descriptions" for the relation between pin values and interface selection. serial interface the transfer timing is indicated in the figure. address/data transfers begin when the cs pin is at a "l" level and end when it changes to a "h" level. because the MSM9225 has an address increment function, the basic transfer consists of "1 address + multiple data." therefore, to access a nonconsecutive address, the cs must be first pulled to a "h" level, and then the address reset. perform address/data transfers lsb first, in 8-byte units. during a transfer, an interval (wait) is necessary between address and data and between consecutive data transfers. (refer to the section, electrical characteristics, for interval values.) note that the wait signal is only generated during the interval between address and data transfers. (1) data write data write operations are performed with the follwing procedure. after setting the cs pin and prd /sr w pin to "l" levels, input an address to the sdi pin. synchronized to the rising edge of synchronous clock sclk, the MSM9225 captures the address in an internal register. when 8 sclk clocks are received, the MSM9225 loads the address into the internal address counter and waits for data reception. next, input data to the sdi pin. an internal register captures data in a similar manner to the address capture, at the rising edge of sclk. when 8 bits of data have been captured, the MSM9225 writes the data to the internal memory or register specified by the address that was received previously, and then increments the counter by 1. if data is to be written to consecutive addresses, continue the data transfer. after all data has been transferred, set the cs pin to a "h" level. (2) data read data read operations are performed with the following procedure. after setting the cs pin to a "l" level and the prd sr w pin to a "h" level, in the same manner as for the data write operation, input an address to the sdi pin. when 8 sclk clocks are received, the MSM9225 loads the address into the internal address counter, reads data from the internal memory or register specified by the address, latches data into a shift register for data output and increments the address counter. then, when sclk is input, latched data is output from the sdo pin synchronized to the falling edge of sclk. at this time, the contents of the data input from the sdi pin does not matter. if there exists remaining data to be read, input another 8 sclk clocks. after all the data (at consecutive addresses) has been read, set the cs pin to a "h" level. if the count value overflows (exceeds xfh), without changing the upper 4 bits of the address, the address increment function will reset the count value of the lower 4 bits to 0, and will continue counting.
? semiconductor MSM9225 40/73 a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 sdi sclk cs sdo r/ w wait address reception internal processing interval data reception internal processing interval data reception (data write & address + 1) internal processing interval (data write & address + 1) a0 a1 a2 a3 a4 a5 a6 a7 * * * * * * * * * * * * * * * * sdi sclk cs r/ w wait address reception data transmission internal processing interval data transmission (data read & address +1 ) internal processing interval (data read & address + 1) (hiz) * * * * * * * * d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 sdo internal processing interval (data read & address + 1) *: don't care (1) data write timing (2) data read timing figure: serial interface transfer timing
? semiconductor MSM9225 41/73 parallel interface the following three types of parallel interfaces are available. (1) address/data separate bus type, no address latch signal (2) address/data separate bus type, with address latch signal (3) multiplexed bus type for transfer timings, refer to the timing diagrams for electrical characteristics.
? semiconductor MSM9225 42/73 MSM9225 connection examples microcontroller interface (1) address/data separate bus (no address latch signal) MSM9225 microcontroller int cs pale prd /sr w pwr prdy /swait a7-0 ad7-0/d7-0 sdo sdi sclk reset xt xt mode1 mode0 int cs rd wr wait a7-0 d7-0 reset 100 k w 11 10 27 9 26 16 4-1, 44-41 38-31 5 7 8 25 reset signal 13 14 30 29 if the clock is supplied externally,in the same manner as for the serial interface, input the clock to the xt pin and leave the xt pin open. 10 k w +5 v cst16mxw040 (2) address/data separate bus (with address latch signal) MSM9225 microcontroller int cs pale prd /sr w pwr prdy /swait a7-0 ad7-0/d7-0 sdo sdi xt xt int cs rd wr wait a7-0 d7-0 reset 100 k w 11 10 27 9 26 16 4-1, 44-41 38-31 5 7 8 25 reset signal 13 14 30 29 ale 10 k w +5 v cst16mxw040 reset mode0 sclk mode1
? semiconductor MSM9225 43/73 (3) address/data multiplexed bus MSM9225 microcontroller int cs pale prd /sr w pwr prdy /swait a7-0 ad7-0/d7-0 sdo sdi xt xt int cs rd wr wait ad7-0 reset 100 k w 11 10 27 9 26 16 4-1, 44-41 38-31 5 7 8 25 reset signal 13 14 30 29 ale 10 k w +5 v cst16mxw040 reset mode0 sclk mode1 (4) serial interface MSM9225 microcontroller int cs pale prd /sr w pwr prdy /swait a7-0 ad7-0/d7-0 sdo sdi xt xt int cs rd wr wait reset 100 k w 11 10 27 9 26 16 4-1, 44-41 38-31 5 7 8 25 reset si g nal 13 14 30 29 ale 10 k w +5 v reset mode0 sclk mode1 sdin sdout sclk open clk if self-excitation is used, in the same manner as for the separate bus, connect an external oscillator.
? semiconductor MSM9225 44/73 can bus interface (1) electrically isolated from bus transceiver (pca82c250) MSM9225 rx1 19 6.8 k w 3.6 k w rx0 18 tx0 22 tx1 23 open pca82c250 v cc 3 canh 7 rs 8 vref 5 open rxd txd 6n137 o.p. cath 4 open 1 open 3 gnd 5 e 7 v cc 8 390 w 2 anode 390 w 1 390 w 4 390 w 0.1 m f 4 1 open open 6 2 8 7 5 0.1 m f 3 6n137 gnd 2 0.1 m f canl 6 124 w 124 w can bus line 470 k w +5 v 6 (2) directly connected to bus transceiver (pca82c250) MSM9225 rx1 19 rx0 18 tx0 22 tx1 23 open pca82c250 v cc 3 canh 7 rxd txd 1 4 gnd 2 0.1 m f canl 6 124 w 124 w vref 5 can bus line rs 8 470 k w from microcontroller (port pin) (normal "l" output)
? semiconductor MSM9225 45/73 (3) monitoring the can bus 23 open pca82c252 canh 11 canl 12 can bus line v cc 10 gnd 13 rth 8 rtl 9 rxd 3 inh 1 txd 2 en 6 nerr 4 stb 5 port port port tx0 tx1 rx0 22 18 rx1 19 battery +5 v microcontroller MSM9225 bat 14 wake 7
? semiconductor MSM9225 46/73 protocol the can (controller area network) is a high-speed multiplexed communication protocol designed to perform real-time communication inside an automobile. can specifications are broadly classified into two layers, the physical layer and the data link layer. the data link layer consists of logical link control and medium access control. the configuration of each layer is listed below. application layer (not including object) data link layer ? logical link control (llc): message and status handling ? medium access control (mac): as per protocol physical layer: signal level and bit representation upper lower protocol mode function (1) standard format mode 2032 types of identifiers can be set in this mode. since the identifier is 11 bits, 2032 types of messages can be handled. (2) extended format mode 2032 2 18 types of identifiers can be set in this mode. in the standard format mode, the identifier is 11 bits. however, in the extended format mode, the identifier is extended to 29 bits (11 + 18). if the srr and ide bits of the arbitration field are both "recessive", the mode changes to the extended format mode. if remote frames for an extended format mode message and a standard format message are transmit simultaneously, the node that transmit the extended format message will change to the receive state. message format can protocol messages have the following 4 types of frames. (1) data frame : transmit data frame (2) remote frame : transmit request frame from the receive side (3) error frame : frame that is output when an error is detected (4) overload frame : frame that is output when the receive side has not completed preparing for reception * in a wired-or logic circuit, the stronger value is defined as "dominant" and the weaker value as "recessive". in figures hereafter, dominant (abbreviation: d) = 0, and recessive (abbreviation: r) = 1.
? semiconductor MSM9225 47/73 1. data frame and remote frame (1) data frame the data frame is for data transmission and consists of 8 fields. r d 12 3 4 5 678 data frame interframe space end-of-frame ack field crc field data field control field arbitration field start-of-frame (2) remote frame this frame is transmit when the receive node requests transmission. the data field is deleted from the data frame and the rtr bit of the arbitration field is made "recessive". r d 12 3 5 678 remote frame interframe space end-of-frame ack field crc field control field arbitration field start-of-frame * even when the data length code of the control field is nonzero, there will be no data frame transfer.
? semiconductor MSM9225 48/73 (3) description of each frame (a) start-of-frame start-of-frame indicates the beginning of a data frame or remote frame and is one dominant bit. start-of-frame r d 1 bit (interframe space or bus idle) (arbitration field) the start-of-frame begins when the bus line level changes. if "dominant" is detected at the sample point, reception continues. if "recessive" is detected at the sample point, the bus becomes idle. (b) arbitration field this field sets priority and data frame/remote frame protocol modes. the arbitration field consists of an identifier, rtr bit, and extended format setting bits. arbitration field r d rtr ( 1 bit ) (control field) identifier id28 id18 ide (r1) ( 1 bit ) r0 (11 bits) standard format mode arbitration field r d rtr ( 1 bit ) (control field) identifier id17 id0 r1 r0 (18 bits) extended format mode srr ( 1 bit ) ide ( 1 bit ) identifier id28 id18 (11 bits) * notes: id28 to id0 is the identifier. the identifier is transmitted msb first. it is prohibited to set the identifier = 1111111xxxxx.
? semiconductor MSM9225 49/73 protocol mode standard format mode extended format mode no. of bits 11 bits 29 bits (c) control field the control field sets the number of data bytes (n) in the data field. (n: 0 to 8) r1 and r0 are fixed as "dominant". the number of bytes is set with dlc3 to dlc0. r d r1 ( ide ) control field rtr r0 dlc3 (arbitration field) dlc2 dlc1 dlc0 (data field) during the standard format mode, the r1 bit and ide bit of the arbitration field are the same bit. number of identifier bits rtr bit setting rtr bit dominant recessive frame type data frame remote frame mode setting protocol mode standard format mode extended format mode srr bit none recessive dominant recessive ide bit
? semiconductor MSM9225 50/73 ? the polynominal p(x) that generates the 15-bit crc is expressed as follows. p(x) = x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 ? the transmit node transmits a crc sequence computed from all basic data bits of the start-of- frame, arbitration field, control field, and data field, without bit stuffing. ? the receive node, compares the crc sequence computed from data bits of the received data (excluding stuff bits) with the crc sequence in the crc field. if they do not match, the node switches to an error frame. dlc3 dlc2 dlc1 dlc0 0000 0001 ???? ???? 0111 1000 data length code 0 1 ? ? 7 8 no. of data bytes data length code setting * in the case of a remote frame, even when the data length code 1 0, there is no data field. (d) data field the data field contains the number of data groups set by the control field. a maximum of 8 data groups can be set. 8 bits form 1 data group. (msb first) r d data field data ( 8 bits ) (control field) data ( 8 bits ) (crc field) (e) crc field a 15-bit crc sequence checks for transmission errors. the crc field consists of a 15-bit crc sequence and a 1-bit crc delimiter. r d crc field crc sequence (15 bits) (data field, control field) crc delimiter ( 1 bit ) ack field
? semiconductor MSM9225 51/73 (f) ack field the field verifies correct reception. the ack field consists of a 1-bit ack slot and a 1-bit ack delimiter. r d ack field ack slot ( 1 bit ) (crc field) (ebd-of-frame) ack delimiter ( 1 bit ) if the receive node detects an error between the start-of-frame and the crc field, ack slot = "recessive" is output. if an error is not detected, ack slot = "dominant" is output. the transmit node outputs 2 "recessive" bits, and verifies the reception status of the receive node. (g) end-of-frame this frame indicates the completion of transmission or reception. the end-of-frame consists of 7 "recessive" bits. r d end-of-frame ( 7 bits ) (ack field) (interframe space or overload frame) (h) interframe space the interframe space is inserted between the data frame, remote frame, error frame, and overload frame and the next frame. the interframe space indicates the separation between frames. output is prohibited during intermission. ? error active: the interframe space consists of a 3- or 2-bit intermission and bus idle. r d interframe space intermission (3/2 bits) (each frame) bus idle (0 to bits) (each frame) ? error passive: the interframe space consists of intermission, suspend transmission, and bus idle. r d interframe space intermission (3/2 bits) (each frame) suspend transmission (8 bits) bus idle (0 to bits) (each frame)
? semiconductor MSM9225 52/73 intermission bit length protocol mode bit length 3 bits standard format mode error status and operation error active errpr passive when the bus becomes idle, each node is able to transmit. the node with a transmit request begins to transmit. after bus idle has continued for 8 bits, transmission becomes possible. if another node begins transmission while the bus is idle, the node changes to reception. error status operation operation when the 3rd intermission bit is "dominant" bus idle: state where bus is not being used by any node. no transmit hold transmit hold evaluated as a start-of-frame output from another node. reception is performed. evaluated as a start-of-frame from own node. the identifier is transmit. transmit status operation
? semiconductor MSM9225 53/73 2. error frame when an error occurs, the node that detected the error will output this frame. while a passive error flag is being output, if another node outputs "dominant", the passive error flag will not end until 6 consecutive bits at the same level are detected. if 6 consecutive bits are "recessive" but the 7th bit is "dominant", the error flag will end after the bit level changes to "recessive". r d 1 2 3 (5) error frame interframe space of overload frame error delimiter error flag error flag error bit (4) field definitions no. error flag error flag error delimiter error bit interframe space/ overload frame name no. of bits difinition error active node: outputs 6 consecutive "dominant" bits. error passive node: outputs 6 consecutive "recessive bits". the node that has received an "error flag" detects a bit stuff error and outputs an "error flag" again. outputs 8 consecutive "receive" bits. if the 8th bit is observed to be "dominant", an overload frame is transmit biginning at the next bit. output following the bit in which an error occurred. (in the case of a crc error, this field is output following the ack delimiter.) "interframe space" or "overload frame" continues. 1 2 3 4 5 6 0 to 6 8 3/10 20 max
? semiconductor MSM9225 54/73 3. overload frame when reception preparations are not complete, the receive node outputs this frame from the 1st intermission bit. if a bit error is detected during intermission, this frame is output from the next bit after a bit error is detected. field definitions r d 1 2 3 (5) overload frame interframe space or overload frame overload delimiter overload flag (node n) overload flag (node m) each frame (4) no. overload flag from node m overload flag from node n overload delimiter each frame interframe space/ overload frame name no. of bits difinition outputs 6 consecutive "dominant" bits. the overload flag is output because node m has not finished reception preparations. having received an "overload flag" during an "interframe space", node n outputs an overload flag. outputs 8 consecutive "recessive" bits. if the 8th bit is observed to be "dominant", an overload frame is transmit biginning at the next bit. output following end-of-frame, error delimiter, and overload delimiter. "interframe space" or "overload frame" continues. 1 2 3 4 5 6 0 to 6 8 3/10 20 max
? semiconductor MSM9225 55/73 functions 1. bus priority decisions (1) when a single node has started transmission while the bus is idle, the node that outputs data first will transmit. (2) when multiple nodes have started transmission beginning from the 1st bit of the arbitration field, the node that outputs the longest consecutive string of "dominant" bits will have priority. (since the bus has a wired-or configuration, "dominant" is strong.) the transmit node compares the arbitration field that it has output with the data levels on the bus. non-matching levels matching levels data output is terminated from the next bit after non-matching is detedted. the operation changes to reception. transmission continues. (3) data frame and remote frame priority if a data frame and remote frame contend for control of the bus, the data frame whose last bit, rtr, is "dominant" will be given priority. 2. bit stuffing if 5 or more consecutive bits have the same level, bit stuffing prevents a burst error by appending 1 bit of inverted data, and then re-synchronizing. reception transmission when receiving a data frame or a remote frame, if there are 5 consecutive bits with the same level between the start-of-frame and the crc field, the next bit is deleted and the data received when transmitting a data frame or remote frame, if there are 5 consecutive bits with the same level between the start-of-frame and the crc field, 1-bit of data at the inverted level of the previous 5 bits is inserted before the next bit. 3. multi-master so that bus priority can be determined by the identifier, any node may become the bus master. 4. multi-cast there is one transmit node, however since multiple nodes can be set with the same identifier, multiple nodes can simultaneously receive the same data. 5. sleep and stop mode functions these modes are low-power consuming standby modes. setting the sleep bit of the stby register to "1" sets the sleep mode. (after bus idle) setting the stop bit of the stby register to "1" sets the stop mode. (after bus idle) the sleep mode is released when the rx0 and rx1 differential inputs, the reset pin input, or the cs pin input is at a "l" level. the stop mode is released when the reset pin input or the cs pin input is at a "l" level.
? semiconductor MSM9225 56/73 6. error control functions (1) types of errors type of error detection method detection condition transmit/receive field/frame error description detection state bits that output data onto the bus, start-of-frame to end-of- frame, error frame, and overload frame transmit/receive node bit error comparison of output level and bus level (excluding stuff bits) both levels do not match start-of-frame to crc saquence transmit/receive node stuff error verify received data with the stuff bit same level of data for 6 consecutive bits start-of-frame to data field receive node crc error crc generated from received data compared to received crc sequence crc's do not match crc delimiter ? ack field ? end-of-frame ? error frame ? overload frame receive node form error verify fixed format field/frame detection of fixed format violation ack slot transmit node ack error verify ack slot by transmit node detection of a "recessive" bit during ack slot (2) error frame output timing type of error bit error, stuff error, form error, ack error crc error error frame is output at the next bit after the error is detected. error frame is output at the next bit after the ack delimiter. output timing (3) procedure when an error is generated after the error frame, the transmit node retransmits a data frame or a remote frame.
? semiconductor MSM9225 57/73 (4) error states (a) types of error states ? there are three types of error states: error active, error passive, and bus off. ? error states are managed by the transmit error counter and the receive error counter. ? each error state is classified according to the error counter value. ? the error flag that is output differs depending upon whether the error state is a transmit or receive operation ? if the value of the error counter is 96 or greater, the bus may be heavily damaged. the bus must be tested for this condition. ? if only one node is active at startup, even if data is transmit an ack will not be returned. therefore, error frame and data retransmission are repeated. in this case, the bus off state will not be entered. even if an error state is repeated at the node that transmits messages, the bus off state will not be entered. ? after reset and after the sleep mode wakes up, the error passive state continues until ack is received. regardless of the number of errors that occur, the transmit error counter will be 255. ? reception can be performed even if transmission is in the bus off state. type of error state operation error counter value type of error flag to be output error active transmit/receive from 0 to 127 active error flag (6 consecutive "dominant" bits) error passive transmit from 128 to 255 passive error flag (6 consecutive "recessive" bits) bus off transmit 256 or greater communication not possible. if 11 consecutive "recessive" bits occur 128 times, then when the error counter = 0, the state can return to error active. receive 128 or greater receive no bus off (b) error counter the error counter is incremented when errors occur and is decremented when transmission or reception is performed correctly. timing of the increment or decrement occurs at the 1st bit of the error flag.
? semiconductor MSM9225 58/73 receive error counter transmit error counter state +1 no change receive node has detected an error (excluding bit errors within the active error flag or overload flag) +8 no change receive node detects "dominant" after error flag output of error frame no change +8 transmit node transmits error flag [when error counter = 0] (1) error passive state and ack error detected, but "dominant" not detected in passive error flag output (2) stuff error occurred during arbitration field no change +8 bit error detected in output of active error flag, overload flag (error active transmit node) +8 no change bit error detected in output of active error flag, overload flag (error active receive node) +8 +8 each node detects 14 consecutive "recessive" bits from the beginning of the active error flag or overload flag, and 8 consecutive "dominant" bits detected thereafter each node detects 8 consecutive "dominant" bits after the passive error flag no change C1 (0 when error counter = 0) transmit node completes transmission without errors (1) C1 (1 rec 127) (2) 0 (rec = 0) (3) set to 127 no change receive node completes reception without errors * rec: receive error counter (c) bit error occurring during intermission overload frame is generated. note) when an error has occured, error control is performed by the error counter at that time. after an error flag is output, the indicated values are added to the error counter.
? semiconductor MSM9225 59/73 7. baud rate control function (1) prescaler the MSM9225 has a prescaler that divides the frequency of the system clock. the prescaler divides the system clock frequency by a factor of 1 to 64 to generate clock ck btl . (btl: bit time logic) (2) bit timing the timing for 1 data bit is defined below. sync segment prop segment phase segment 1 phase segment 2 bit time sampling point definition for can protocol sync segment sjw1 tseg1 tseg2 bit time sampling point definition for MSM9225 sjw2 ? sync segment : this is the first segment for bit synchronization. ? prop segment : this segment absorbs the delay of the output buffer, can bus and input buffer. set the prop segment so that ack will be returned by the start of phase segment 1. prop segment time 3 (output buffer delay) + (can bus delay) + (input buffer delay) ? phase segments : these segments compesate for deviations in the data bit timing. the larger these segments, the greater the allowable deviation, however communication speed will decrease. ? sjw : abbreviation of re synchronization jump width. these bits set the bit synchronization range. segment name segment length (btl) can protocol MSM9225 sync segment (synchronization segment) sync segment (synchronization segment) 1 prop segment (propagation segment) sjw1 1 to 4, programmable tseg1 (time segment) 1 to 16, programmable phase segment 1 (phase buffer segment) tseg2 (time segment) 1 to 8, programmable phase segment 2 (phase buffer segment) sjw2 protocol 1 to 4, programmable
? semiconductor MSM9225 60/73 (3) data bit synchronization since there is no sync signal for the receive node, synchronization is obtained from level changes on the bus. the transmit node transmits data is synchronization with the transmit node bit timing. (a) hardware synchronization hardware synchronizaion is the bit synchronization performed when a receive node in the bus idle state detects a start-of-frame. if a falling edge is detected on the bus, that bit is the sync segment and is followed by the prop segment. in this case, syncronization is obtained without regard for sjw. after reset and after wake up, it is necessary to obtain bit synchronization. therefore, hardware synchronizes to the first bus level change only. start-of-frame bus idle can bus sync segment prop segment phase segment 1 phase segment 2 bit timing (b) bit synchronization if a level change is detected on the bus during receprion, bit synchronization is obtained. there are two methods of synchronization. normal operation: falling edge of level low-speed operation: falling edge and rising edge of level during the bit timing interval specified by sjw, synchronization is obtained only if an edge is detected. the data sampling point of the receive node will move in relation to the shift in baud rate between the transmit node and receive node. the range of allowable "shift" is defined as "sjw". the sjw range is centered on the sync segment and extends both before and after that segment (+/C baud rate). if an edge occurs within the sjw range, synchronization is obtained. if an edge occurs outside the sjw range, synchronization is not obtained. the bit detected at the edge forces the sync segment, and is followed by the prop segment. the bit timing is restarted. later bits previous bits can bus sync segment prop segment phase segment 1 phase segment 2 bit timing sjw
? semiconductor MSM9225 61/73 8. state transition diagrams (1) transmit state transition diagram start-of-frame arbitration field control field data field crc field ack field end-of-frame intermission 1 bit error bit error bit error ack error bit error error frame output bit is "0" but bus level is "1" error bit error overload frame form error bit error complete complete c receive receive a output bit is "1" but bus level is "0" error intermission 2 bus idle initial setting error passive 8 bits of "1" complete rtr = 0 complete complete complete complete start-of-frame reception rece p tion b start-of-frame transmission rtr = 1 error active
? semiconductor MSM9225 62/73 (2) receive state transition diagram start-of-frame arbitration field control field data field crc field ack field end-of-frame intermission 1 stuff error stuff error crc error stuff error error frame bit error overload frame form error preparation not complete complete complete b transmit bus idle initial setting complete rtr = 0 complete complete complete complete start-of-frame transmission transmission c start-of-frame reception rtr = 1 a transmit stuff error form error bit error form error bit error preparation not complete
? semiconductor MSM9225 63/73 (3) error state transition diagram (a) transmit error active error passive bus off tec 3 128 11 consecutive bits are "1", occurs 128 times tec 3 256 0 tec 127 128 tec 255 tec 3 256 tec 127 tec = 0 *tec: transmit error counter (b) receive error active error passive rec 3 128 reception successful 0 rec 127 128 rec 255 rec = 127 *rec: receive error counter
? semiconductor MSM9225 64/73 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ta = 25c C0.3 to +7.0 v av dd C0.3 to +7.0 (av dd = v dd ) v input voltage v i C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 v power dissipation p d ta 25c mw operating temperature t op C40 to +115 c storage temperature t stg C65 to +150 c 615 recommended operating conditions parameter symbol condition min. power supply voltage v dd 4.5 operating temperature t op C40 v dd = av dd typ. 5.0 +25 max. 5.5 +115 unit v c
? semiconductor MSM9225 65/73 electrical characteristics dc characteristics parameter symbol applicable pin max. unit "h" input voltage v ih v dd + 0.3 v "l" input voltage v il +0.2v dd v "h" input current i ih1 applies to all inputs m a i ih2 +1.0 m a "l" input current i il1 C3 m a i il2 +1.0 m a "h" output voltage v oh1 v v oh2 v "l" output voltage v ol1 0.4 v v ol2 0.4 v output leakage current i ih1 +1.0 m a dynamic supply current i dd 15 ma static supply current i dds 100 m a min. 0.8v dd C0.3 C1.0 C25 C1.0 v dd C 1.0 v dd C 1.0 C1.0 25 3 (v dd = av dd = 4.5 to 5.5 v, ta = C40 to +115c) applies to all inputs xt other inputs xt other inputs int , prdy /swait ad7-0/d7-0 int , prdy /swait ad7-0/d7-0 prdy /swait, ad7-0/d7-0 condition v i = v dd v i = 0 v i oh1 = C80 m a i oh2 = C400 m a i ol1 = 1.6 ma i ol2 = 3.2 ma v i = v dd /0 v f osc = 16 mhz, no load sleep/stop mode rx0, rx1 characteristics parameter symbol condition max. unit input voltage vr xi av dd C 1.5 v input offset voltage v off +20 mv min. 0.5 C20 (v dd = av dd = 4.5 to 5.5 v, ta = C40 to +115c) input leakage current i lk +10 m a av dd supply current ai dd 4ma C10 tx0, tx1 characteristics parameter symbol condition max. unit "h" output voltage v oh v v oh v i oh = C3.0 ma min. av dd C 0.4 av dd C 1.0 (v dd = av dd = 4.5 to 5.5 v, ta = C40 to +115c) i oh = C6.0 ma "l" output voltage v ol 0.4 v v ol 1.0 v i ol = 10.0 ma i ol = 20.0 ma
? semiconductor MSM9225 66/73 ac characteristics parallel mode parameter symbol condition max unit ale address setup time t as ns ale address hold time min 10 10 (v dd = av dd = 4.5 to 5.5 v, ta = C40 to +115c, f osc = 16 mhz) prd output data delay time 40 prd output data hold time 5 ale "h" level width 20 access cycle time 4t address hold time from prd 10 ale delay time from prd 20 prd "h" level width 20 prdy "l" delay time 35 prdy "h" delay time 2.5t + 35 input data setup time 30 input data hold time 5 pwr delay time 10 address hold time from pwr 20 ale delay time from pwr 20 pwr "h" level width 40 pwr "l" level width 20 cs delay time from prd 0 cs delay time from pwr 0 t ah t rdly t rdh t waleh t cyc t rah t hra t wrdh t arldly t arhdly t wds t wdh t ws t wah t hwa t wrh t wrl t hrc t hwc ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns serial mode parameter symbol condition max unit cs setup time t cs ns cs hold time min 10 8t (v dd = av dd = 4.5 to 5.5 v, ta = C40 to +115c, f osc = 16 mhz) sclk cycle sclk pulse width 167 83 sdi setup time 30 sdi hold time 5 sdo output enable time 30 sdo output disable time 30 sdo output delay time 30 sr w setup time 10 sr w hold time 0 swait output delay time 2t swait "h" level width 6t byte delay 8t t ch t cp t cw t ds t dh t csodly t cszdly t pd t rs t rh t srdly t wrdy t wait ns ns ns ns ns ns ns ns ns ns ns ns ns
? semiconductor MSM9225 67/73 other timing characteristics parameter symbol condition max. unit system clock cycle t clkcy ns reset "h" level input width min. 62 5 (v dd = av dd = 4.5 to 5.5 v, ta = C40 to +115c) reset "l" level input width int "l" level output width 5 32t t wrsth t wrstl t wintl m s m s ns (*) t = 1/f osc
? semiconductor MSM9225 68/73 timing diagrams separate bus mode read access timing t cyc t rah t wrdh t rdh t arldly t arhdly t rdly t ws t hrc cs a7-0 ad7-0/ d7-0 prd /sr w prdy /swait write access timing t cyc t wah t wrh t wds t arldly t arhdly t wrl t ws t hwc cs a7-0 ad7-0/ d7-0 pwr prdy /swait t wdh
? semiconductor MSM9225 69/73 separate bus/address latch mode read access timing t cyc t rah t wrdh t arldly t arhdly t rdly t waleh t hrc cs a7-0 ad7-0/ d7-0 prd /sr w prdy /swait t rdh t hra t as pale write access timing t cyc t wah t wrh t arldly t arhdly t ws t waleh t hwc cs a7-0 ad7-0/ d7-0 pwr prdy /swait t wds t hwa t as pale t wrl t wdh
? semiconductor MSM9225 70/73 multiplexed bus mode read access timing t cyc t wrdh t arldly t arhdly t rdly t waleh t hrc cs ad7-0/ d7-0 prd /sr w prdy /swait t rdh t hra t as pale t ah write access timing t cyc t wrh t arldly t arhdly t ws t waleh t hwc cs ad7-0/ d7-0 pwr prdy /swait t wdh t hwa t as pale t ah t wds t wrl
? semiconductor MSM9225 71/73 serial mode read access timing t wrdy cs t cs t cp t cw t cw t dh t ds a0 a1 a6 a7 t wait don't care t ch t pd t cszdly t csodly dmy0 dmy1 dmy6 dmy7 d0 t rh t rs t srdly sclk sdi sdo prd /sr w prdy /swait write timing t wrdy cs t cs t cp t cw t cw t dh t ds a0 a1 a6 a7 t wait t ch t rh t rs t srdly sclk sdi sdo prd /sr w prdy /swait (hiz) a0
? semiconductor MSM9225 72/73 other timings t wrstl reset t wrsth t wintl int t clkcy clk (xt) t clkcy
? semiconductor MSM9225 73/73 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.41 typ. qfp44-p-910-0.80-2k mirror finish
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-11

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